CVE-2025-0647
High
Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
SeverityHigh
CVSS7.9
Exploit probability—
Product
Arm C1-ultra Firmware
PublishedJan 14, 2026
First seenJan 14, 2026
Weakness typeCWE-226CWE-226
How to fix
Sources list no fixed version or patch link for this vulnerability.
Affected products
| Product | Affected versions | Fixed in |
|---|---|---|
| arm c1-ultra_firmware | No range specified | — |
| arm c1-premium_firmware | No range specified | — |
| arm cortex-a710_firmware | No range specified | — |
| arm cortex-x2_firmware | No range specified | — |
| arm cortex-x3_firmware | No range specified | — |
| arm cortex-x4_firmware | No range specified | — |
| arm cortex-x925_firmware | No range specified | — |
| arm neoverse-v2_firmware | No range specified | — |
| arm neoverse-v3_firmware | No range specified | — |
| arm neoverse-v3ae_firmware | No range specified | — |
| arm neoverse-n2_firmware | No range specified | — |
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