CVE-2025-45006
Critical
Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
SeverityCritical
CVSS9.1
Exploit probability—
ProductRISC-V Processor
PublishedJul 1, 2025
First seenJul 1, 2025
Weakness typeCWE-266CWE-266
How to fix
Sources list no fixed version or patch link for this vulnerability.
Affected products
| Product | Affected versions | Fixed in |
|---|---|---|
| Open-Source RISC-V Processor | No range specified | — |
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